In relatively large computer systems the main memory is typically subdivided into a group of arrays or planes. This subdivision of the memory provides easier addressing and control. However, the actual transfer of data into and out of the memory planes can present several problems. In particular the tying together of numerous memory output terminals can create a substantial timing problem that significantly reduces the speed of the memory. Further, for dynamic memories, there must be periodic refreshing of the memory arrays, but this can frequently conflict with the transfer of data to and from the memory. In some refresh situations the data can actually be lost thereby requiring an additional memory cycle following the refresh.
In view of the above problems involving multiple plane memories, there exists a need for a configuration for a memory array unit in which the transfer of data to and from the memory array is not subject to timing problems and is further compatible with refresh cycles without the danger of losing data.